In a power amplifier for use in a radio communication system, linearity and high efficiency are required. Especially, in recent years, there is often handled a signal having an average value of signal amplitudes which is largely different from a maximum amplitude in a multi-valued digital modulation communicating system or the like. In a case where such signal is amplified with a conventional power amplifier, the amplifier is set to an operation point at which the signal can be amplified to the maximum amplitude without straining the signal. Therefore, there is little time when the amplifier operates in the vicinity of a saturated output in which a relatively high efficiency can be maintained. In general, the efficiency of the amplifier is low.
To solve this problem, various technologies have been developed in which the efficiency of the amplifier is improved while maintaining the linearity. One of them relates to the Doherty amplifier. A basic structure of the Doherty amplifier is already known to a person skilled in the art (refer to “A New High Efficiency Power Amplifier for Modulated Waves” authored by W. H. Doherty, 1936 Proc. of IRE, Vol. 24, No. 9, pp. 1163 to 1182 and “Advanced Techniques in RF Power Amplifier Design” authored by Steve C. Cripps, Artech House 2002, pp. 33 to 56).
Moreover, an expansion type Doherty amplifier described later is also known (refer to “A Fully Matched N-way Doherty Amplifier with Optimized Linearity” authored by Youngoo Yang, Jeonghyeon Cha, Bumjae Shin, and Bumman Kim, IEEE Trans. MTT, Vol. 51, No. 3, Mar. 2003).
The Doherty amplifier has an amplifier which operates while maintaining saturation in the vicinity of the saturated output power. Accordingly, an efficiency which is higher than that of a usual A-class or AB-class amplifier is realized even at a time when the saturated power backs off.
FIG. 4 is a structure diagram showing one example of the conventional Doherty amplifier.
The drawing schematically shows the amplifier described in Japanese Patent Application Publication No. 10-513631 (refer to abstract and FIG. 6).
Referring to the drawing, the conventional Doherty amplifier has: a carrier amplifier 21 that performs a signal amplifying operation at all times; a peak amplifier 22 (sometimes referred to as an “auxiliary amplifier”, but unified as the “peak amplifier” in the present invention) that operates only at a time of the outputting of a high electric power; a combiner 23 that combines and outputs the outputs from the carrier amplifier 21 and the peak amplifier 22; and a distributor 24 that distributes an input signal to the carrier amplifier 21 and the peak amplifier 22. The carrier amplifier 21 is included in a single package 25, and the peak amplifier 22 is included in a different package 26.
In the carrier amplifier 21, an amplifier biased in the AB-class or a B-class is normally used. The peak amplifier 22 is usually biased and used in a C-class so as to operate only when the signal electric power is a high output. The combiner 23 which combines the outputs of the carrier amplifier 21 and the peak amplifier 22 is structured by a transformer, an impedance converter and the like. The combiner is usually structured by a ¼ wavelength transmission line in a case where a signal having a microwave band is handled. The input distributor 24 is structured by a ¼ wavelength transmission line, a 90° hybrid circuit or the like in order to set a phase relation between the output signals of the peak amplifier 22 and the carrier amplifier 21 so that the signals are combined in the same phase at a signal combining point of the combiner 23.
As described above, the carrier amplifier 21 and the peak amplifier 22 which are constituting elements of such Doherty amplifier have been structured by using amplification elements (1 package transistor) which have been heretofore separately packaged.
As one example, the carrier amplifier 21 and the peak amplifier 22 have been structured by using two MOS type FET semiconductor elements each of which is MRFI 83 (field effect transistor of Motorola, Inc.).
With such a structure, since the transistors stored in the separate packages are used in the respective amplifiers, an area for mounting two packages of transistors is required. This has been disadvantageous in advancing miniaturization of a device.
Moreover, since two amplifiers are separately disposed, the transmission line lengthens which extends from each amplifier output to the signal combining point, transmission losses increases, and the efficiency of the whole amplifier is lowered. The structure is also disadvantageous in reducing costs of the device.
Furthermore, in the linear amplifier of A-class, AB-class, B-class or the like structured as a push-pull amplifier or a balance amplifier, there is little time when the electric power amplifier operates in the vicinity of the saturated output in which the relatively high efficiency can be maintained as described above. Therefore, in general, the efficiency is low, and there has been a demand for an electric power amplifier which operates with a higher efficiency.
It is therefore an object of the present invention to provide an amplifier which can achieve miniaturization of a device, reduction of transmission losses, and improvement of an efficiency.